Semiconductor Measurement Technology: The Design, Testing, and Analysis of a Comprehensive Test Pattern for Measuring CMOS/SOS Process Performance and Control

摘要

A Process Validation Wafer (PVW) is a wafer containing only test patterns. One PVW accompanies a product lot during the fabrication process. Test patterns NBS-16 and NBS-26 are designed to be used on PVWs. They contain both process parameter test structures and random fault test structures. Eighteen NBS-16 PVWs were fabricated in a radiation-hardened silicon-gate CMOS/SOS process. These PVWs were tested on a high-speed computer-controlled dc test system. Test results from the process parameter test structures were used to establish the baseline electrical parameters for each product lot and to produce an eight-level gray scale wafer map for these parameters. Based on correlations of selected wafer maps, it was possible to identify specific yield-related process problems otherwise unknown to the manufacturer or user. Test results from two random fault test structures were used to establish a statistically significant data base for identifying and evaluating major yield-limiting fault mechanisms in the process. Test results from a developmental random access fault structure and a gate dielectric integrity array are presented. The results are analyzed for selected PVWs and a major yield-limiting fault mechanism detected.