Design and Layout of a Complementary Metal Oxide Semiconductor Silicon on Sapphire Cell Library

摘要

A method was developed for designing CMOS/SOS circuits using computer-aided design tools. CMOS/SOS fabrication methods and theory of operation as well as differences between CMOS/SOS and bulk CMOS were researched. SPICE was used to determine optimum gate width-to-length ratios resulting in symmetrical transitional delays. Two designs were developed to implement the CMOS/SOS programmable logic array (PLA), and a C program was written to automatically generate one of the designs by means of a file formatted in Caltech Intermediate Form (CIF). Basic logic gates were designed as part of a small CMOS/SOS standard cell library, and a medium scale integration (MSI) arithmetic logic unit (ALU) was developed using cells from the library. An analysis was made of significant differences between a NMOS PLA developed by Standford and the CMOS/SOS PLA. According to SPICE results, the CMOS/SOS PLA exhibited slightly faster switching speeds and greatly reduced power dissipation. CMOS/SOS circuits required significantly larger layouts than similar NMOS circuits.