Ferroelectric, stacked gate FETs: A prospective for planar CMOS with reduced leakage current and Sub-kT/q subthreshold swing

摘要

The planar silicon-on-insulator (SOI) based metal-oxide semiconductor (MOS) structure has been at the center of attention of researchers who are attempting to extend its scalability. This study presents an analysis of ferroelectric MOS field effect transis-tors (Fe-MOSFETs) based on the surface potential, threshold voltage, subthreshold swing, leakage current, ON current and electron temperature. In addition, the electro-static integrity (EI) factor and the threshold-voltage-to-swing ratio for Fe-MOSFETs were estimated and compared with those of conventional, high-k and double-gate (DG) MOSFETs. The analysis shows that the Fe-MOSFET is able to enhance the scalability and fulfil the expectation of researchers studying planar complementary MOS (CMOS) devices.