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Reduced gate leakage current in thin gate dielectric CMOS integrated circuits
Reduced gate leakage current in thin gate dielectric CMOS integrated circuits
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机译:降低薄栅介质CMOS集成电路中的栅极泄漏电流
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摘要
The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for the MOS capacitor such that the capacitor area and leakage current constraints are satisfied. The MOS capacitor is not biased in inversion.
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