首页> 外国专利> Semiconductor integrated circuit device having a leakage current cutoff circuit, constructed using MT-CMOS, for reducing standby leakage current

Semiconductor integrated circuit device having a leakage current cutoff circuit, constructed using MT-CMOS, for reducing standby leakage current

机译:具有使用MT-CMOS构造的漏电流截止电路的半导体集成电路器件,用于减小待机漏电流

摘要

A semiconductor integrated circuit device has a high-threshold N-channel type MIS field effect transistor and a load circuit. The high-threshold N-channel type MIS field effect transistor is connected between a real high-potential power supply line and a pseudo high-potential power supply line. The load circuit has a low-threshold P-channel type MIS field effect transistor and a low-threshold N-channel type MIS field effect transistor. A first power supply terminal of the load circuit is connected to the pseudo high-potential power supply line, and a second power supply terminal of the load circuit is connected to a real low-potential power supply line.
机译:半导体集成电路器件具有高阈值N沟道型MIS场效应晶体管和负载电路。高阈值N沟道型MIS场效应晶体管连接在实际的高电位电源线和伪的高电位电源线之间。负载电路具有低阈值P沟道型MIS场效应晶体管和低阈值N沟道型MIS场效应晶体管。负载电路的第一电源端子连接至伪高电位电源线,并且负载电路的第二电源端子连接至实际低电位电源线。

著录项

  • 公开/公告号US2004070427A1

    专利类型

  • 公开/公告日2004-04-15

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US20030674016

  • 发明设计人 SATORU MIYAGI;

    申请日2003-09-30

  • 分类号H03K3/00;

  • 国家 US

  • 入库时间 2022-08-21 23:20:14

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