Integration of ultrathin (1.6 -- 2.0 nm) RPECVD stacked oxide/oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs.

摘要

The system-on-a-chip concept has gradually become the trend in advanced CMOS technologies. As Integrated Circuits (IC) density is increased, MOS device lateral dimensions should become smaller. As a result, the gate dielectric thickness must be reduced in order to maintain acceptable short-channel effects as the channel length of the MOSFET is reduced and to maximize drain current. As gate lengths are decreased to below 100 nm in advanced ULSI devices, gate dielectrics must be decreased to 2.0 nm or less. SiO₂, the gate dielectric currently used in ULSI devices, shows several significant limitations in this thickness regime such as boron penetration in PMOS devices, high direct tunneling currents and dielectric reliability.; Recent studies have demonstrated that CMOS devices with (i) RPECVD stacked oxide/nitride, (ii) RTCVD stacked oxide/nitride followed by an N₂O RTA, (iii) RTCVD oxynitride gate dielectrics, and (iv) JVD nitride and oxynitride display superior electrical and reliability characteristics with respect to homogeneous oxide gate dielectrics, including reduced leakage current, effective prevention of boron penetration to the Si-dielectric interface and reduced hot carrier degradation.; This dissertation covers the following research areas. First, a quantum-mechanical model is developed to provide a quantitative understanding of the magnitude of the tunneling current through oxide and stacked oxide/nitride gate dielectrics. A comparison between experiments and calculations is made for both homogeneous oxide and stacked oxide/nitride gate dielectrics. Based on the parameters from experiment, this model is used to project the limit of ultrathin stacked oxide/nitride. Secondly, dual gate CMOSFET's with ultrathin control oxides, and stacked oxide/nitride and stacked oxide/oxynitride gate dielectrics formed by Remote Plasma Enhanced Chemical Vapor Deposition (RPECVD) were fabricated. A comprehensive comparison of device performance and reliability is made between PMOSFET and NMOSFETs with these three gate dielectrics. This comparison demonstrates that RPECVD stacked oxide/nitride and stacked oxide/oxynitride provide possible alternatives for use in aggressively-scaled devices. Compared to stacked oxide/nitride dielectrics, stacked oxide/oxynitride dielectrics are a better candidate for use in devices requiring ultrathin gate dielectrics. Finally, performance and reliability data are presented for aggressively-scaled dual gate submicron CMOSFET's with 1.67 nm stacked oxide/oxynitride gate dielectrics, which include an intentional 90-sec interface nitridation at the monolayer level to further reduce leakage current. These devices show excellent performance and as much as 1000 times lower tunneling current as compared to devices with 1.67 nm plasma oxides.