A 0.5 V single power supply operated high-speed boosted andoffset-grounded data storage (BOGS) SRAM cell architecture

摘要

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAMncell architecture which uses a boosted and offset-grounded data storagen(BOGS) scheme. The key target of BOGS is to minimize the charge amountnsupplied from the embedded charge pump circuits, which are required tonboost the effective gate to source voltagen(V0=VGS-VT) up to 0.8 V necessary tonachieve 100 MHz operation even at 0.5 V single power supply. Thus, thenkey low-power strategy of BOGS is “putting the right (highernefficiency) boosted power-supply from charge pump circuit into the rightnposition (less power consumed transistor) in a SRAM cell.” Thisnpaper is focused on why BOGS can realize a greater savings of the chargenamount supplied from the boosted power-line and can reduce the powerndissipation to ⩽1/30.4 and ⩽1/3.9 compared to the previouslynreported negative source-line drive (NSD) scheme and negative word-linendrive (NWD) scheme, respectively, while achieving a 0.5 V/100 MHznoperation