Testing configurable LUT-based FPGA's

摘要

We present a new technique for testing field programmable gatenarrays (FPGA's) based on look-up tables (LUT's). We consider angeneralized structure for the basic FPGA logic element (cell); itnincludes devices such as LUT's, sequential elements (flip-flops),nmultiplexers and control circuitry. We use a hybrid fault model fornthese devices. The model is based on a physical as well as a behavioralncharacterization. This permits detection of all single faults (eithernstuck-at or functional) and some multiple faults using repeated FPGAnreprogramming. We show that different arrangements of disjointnone-dimensional (l-D) cell arrays with cascaded horizontal connectionsnand common vertical input lines provide a good logic testing regimen.nThe testing time is independent of the number of cells in the arrayn(C-testability), We define new conditions for C-testability ofnprogrammable/reconfigurable arrays. These conditions do not suffer fromnlimited I/O pins. Cell configuration affects thencontrollability/observability of the iterative array. We apply thenapproach to various Xilinx FPGA families and compare it to prior work