An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs

摘要

Finite impulse response (FIR) filter is a fundamental element in digital signal processing (DSP) systems. Traditional implementations have been using application specific integrated circuits (ASICs) or DSP processors. However, the increase in logic capacity and versatility of the field programmable gate array (FPGA) platforms has made it possible to realize numerically intense algorithms and thus provide a complete system-on-chip (SoC) solution in a single package. With modern FPGAs fast moving from prototype designing to low and medium volume productions, it becomes imperative to consider architectural optimizations that are specific to FPGAs only. In this paper, for the first time, we attempt to optimize filtering structures by considering the technology-dependent approaches. We present a general procedure that can be used to efficiently map the Boolean networks onto FPGA fabric. Based on this procedure, a technology optimal realization of the multiply-adder unit, which is a fundamental functional unit in FIR filters is presented. Since no such implementation has been reported, we have compared our implementations against the various technology-independent optimizations that have been detailed in prior literature. Further, to give an idea about the performance speed-up achieved with our implementations, we have compared our results against the FIR structures based on the multiply-adder IP v 2.0, inherent in Xilinx FPGAs. A distinctive feature of our implementation is that a simultaneous speed-up is achieved in all three parameters (area, speed and power). This is in contrast to the technology-independent implementations where there is always a performance trade-off between different parameters.