Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device

摘要

Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.