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The design of an SRAM-based field-programmable gate array. I. Architecture

机译:基于SRAM的现场可编程门阵列的设计。一,建筑

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Field-programmable gate arrays (FPGAs) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen, and no information on the circuit-level or physical design of the devices. This paper describes the high-level architectural design of a static-random-access memory programmable FPGA. A forthcoming Part II will address the circuit design issues through to the physical layout. The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built computer-aided design tools. The resulting logic block is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.
机译:现场可编程门阵列(FPGA)现在已广泛用于数字系统的实现,并且有许多商业体系结构可用。尽管文献和数据手册中都包含有关这些架构的详细描述,但是关于如何选择高级架构的信息很少,也没有关于设备的电路级或物理设计的信息。本文介绍了静态随机存取存储器可编程FPGA的高级体系结构设计。即将发布的第二部分将解决电路设计问题直至物理布局。通过对基准电路和定制的计算机辅助设计工具进行实验,确定了FPGA的逻辑块和路由架构。最终的逻辑块是一个四输入查找表的不对称树,这些表被硬连线在一起,并且具有经过仔细选择的段长度分布的分段路由体系结构。

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