The design of a SRAM-based field-programmable gate array-Part II:Circuit design and layout

摘要

For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmablengate arrays (FPGA's) are now widely used for the implementation ofndigital systems, and many commercial architectures are available.nAlthough the literature and data books contain detailed descriptions ofnthese architectures, there is very little information on how thenhigh-level architecture was chosen and no information on thencircuit-level or physical design of the devices. In Part I of thisnpaper, we described the high-level architectural design of a staticnrandom-access memory programmable FPGA. This paper will address thencircuit-design issues through to the physical layout. We addressnarea-speed tradeoffs in the design of the logic block circuits and innthe connections between the logic and the routing structure. Allncommercial FPGA designs are done using full-custom hand layout to obtainnabsolute minimum die sizes. This is both labor and time intensive. Wenpropose a design style with a minitile that contains a portion of allnthe components in the logic tile, resulting in less full-custom effort.nThe minitile is replicated in a 4×4 array to create a macro tile.nThe minitile is optimized for layout density and speed, and isncustomized in the array by adding appropriate vias. This technique alsonpermits easy changing of the hard-wired connections in the logic blocknarchitecture and the segmentation length distribution in the routingnarchitecture