Layout design apparatus of a semiconductor integrated circuit, a manufacturing method of layout design method and layout design program, and a semiconductor integrated circuit device

摘要

PROBLEM TO BE SOLVED: To prevent an increase in a design TAT (Turn Around Time) of semiconductor integrated circuit.;SOLUTION: The layout design device includes: a stress distribution data reading means 3 for reading stress distribution data showing a distribution of stress values of package stress applied to a semiconductor chip caused by a package; an element layout data acquiring means 7 for extracting element layout data from chip layout data of the semiconductor chip; a calibration curve data holding part 9 for holding calibration curve data showing a relation between a stress value and a characteristic fluctuation of an element about each element mounted on the semiconductor chip; an element characteristic fluctuation calculating means 11 for calculating an element characteristic fluctuation due to package stress about each element on the basis of the stress distribution data, the element layout data and the calibration curve data; an element layout correcting means 13 for correcting the element layout data so as to negate the element characteristic fluctuation; and a chip layout correcting means for correcting chip layout data by using corrected element layout data.;COPYRIGHT: (C)2012,JPO&INPIT