The design of an SRAM-based field-programmable gate array. I.Architecture

摘要

Field-programmable gate arrays (FPGAs) are now widely used for thenimplementation of digital systems, and many commercial architectures arenavailable. Although the literature and data books contain detailedndescriptions of these architectures, there is very little information onnhow the high-level architecture was chosen, and no information on thencircuit-level or physical design of the devices. This paper describesnthe high-level architectural design of a static-random-access memorynprogrammable FPGA. A forthcoming Part II will address the circuit designnissues through to the physical layout. The logic block and routingnarchitecture of the FPGA was determined through experimentation withnbenchmark circuits and custom-built computer-aided design tools. Thenresulting logic block is an asymmetric tree of four-input lookup tablesnthat are hard-wired together and a segmented routing architecture with ancarefully chosen segment length distribution