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Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation

机译:高频操作中片上去耦电容的有效性降低

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This paper shows the decreased effectiveness of on-chip decoupling capacitance in high-frequency operation. On-chip decoupling capacitance is often used to decrease the variation of the propagation delay caused by power/ground noise, i.e., dynamic IR-drop and/or delta-I noise. However, it is shown in this paper that decoupling capacitance is only effective for coping with dynamic IR-drop if the recharging time between switching events is sufficient. In other words, the effectiveness of decoupling capacitance for dynamic IR-drop in high-frequency operation is less than that of a fully-charged decoupling capacitor. The recharging time and the effectiveness of a decoupling capacitor depend on the propagation delay of the average circuit path which is used to determine the total switching current of a given macro/chip and clock cycle time. If the propagation delay of the critical paths is approximately equal to that of the average circuit path, then it is shown in this paper that adding decoupling capacitance never improves the maximum frequency of the system due to dynamic IR-drop limitations. On the other hand, if the propagation delay of the critical paths is larger than that of the average circuit path, then the maximum frequency is improved by adding decoupling capacitance. In both cases, a new metric, called the apparent capacitance, can be used to help make correct decisions about decoupling capacitance planning.
机译:本文显示了高频工作中片上去耦电容的有效性下降。片上去耦电容通常用于减少由功率/接地噪声(即动态IR压降和/或delta-I噪声)引起的传播延迟的变化。但是,本文表明,如果开关事件之间的充电时间足够长,则去耦电容仅对应对动态IR降有效。换句话说,用于高频操作中动态IR降的去耦电容的有效性要小于完全充电的去耦电容器的有效性。再充电时间和去耦电容器的有效性取决于平均电路路径的传播延迟,该路径用于确定给定宏/芯片的总开关电流和时钟周期时间。如果关键路径的传播延迟近似等于平均电路路径的传播延迟,则本文表明,由于动态IR压降限制,增加去耦电容永远不会提高系统的最大频率。另一方面,如果关键路径的传播延迟大于平均电路路径的传播延迟,则可以通过增加去耦电容来提高最大频率。在这两种情况下,可以使用称为视在电容的新度量标准来帮助做出有关去耦电容规划的正确决策。

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