METHOD FOR ESTIMATING ON-CHIP DECOUPLING CAPACITANCE OF ASIC BASED ON CHAIN CIRCUIT

摘要

A method for estimating the on-chip decoupling capacitance of ASIC based on the chain circuit is provided. The method involves extracting the parasitic parameters of the post-layout ASIC circuit by the Star-RCXT, and analyzing the SPF file format and the information contained on it by Perl in order to model the chain circuit, and then computing the equivalent capacitance by the Euler's formula, and compressing the circuit according to the Y-Δ transform, and computing the voltage and the current of each node of the compressed circuit, and computing the voltage and the current of each node of the chain circuit by recovering the chain circuit, and computing the number of the required decoupling capacitor by the integration method according to the principle that the fluctuation of the node voltage cannot be more than 10% of the power supply voltage.