The purpose of this dissertation is to demonstrate ways to make GaAs Heterojunction Bipolar Transistor (HBT) Radio Frequency Integrated Circuits (RFIC) more ESD (Electrostatic Discharge) robust. This dissertation starts off with experimental measurement result for the ESD robustness of elements found in GaAs HBT process. How layout and process can affect the ESD robustness of GaAs HBT is examined. This experiment result can be used for sizing of elements in a RFIC, so that RFIC is more ESD robust. This result can be also used for proper sizing of elements for the ESD protection circuits. Next, novel low loading capacitance, ∼0.1 pF, on-chip ESD protection circuits for >2000 Vesd protection for GaAs HBT RFIC that does not degrade RF circuit performance are introduced. Their principle of operation, loading capacitance, leakage current, ESD clamping characteristics, and robustness over process variation and temperature are investigated. The ESD protection circuits are designed that they can be implemented as standard library cells and they can be drop and place ESD protection solution for all the in/out and DC pads. The standard library cells for the ESD protection circuits are so small, a size of a standard bonding pad, that they can be place in the unused area between pads without increasing the die size. Finally, to demonstrate the applications of the ESD protection circuits to RCIC, a 5.4–6.0 GHz power amplifier, which can be used for the 802.11A wireless local area network, and DC-20 GHz broadband distributed amplifier RFIC, which can be used as a transimpedance amplifier (TIA), both of them with ESD protection circuits are fabricated and would be discussed.
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