Susceptibility of On-Chip Protection Circuits to Latent Failures Caused by Electrostatic Discharges

摘要

Among the LSI devices, MOS circuits are highly sensitive to damages due to electrical overstressings (EOS) arising from electrostatic discharges (ESD). Hence, several schemes have been developed for LSI input protection (on-chip) circuits. However, it has been observed that, if repeated, and/or multiple discharges occur, the protection circuits themselves would be cumulatively stressed, with the result that their protection capability will be degraded progressively. At a particular stage, the ineffectiveness of the protection circuit will allow subsequent stress occurrences (zaps) to reach the active MOS regions causing a total device failure. Considering various component-damages (woundings) observed at the protection networks, the cumulative degradation at low or subcatastrophic thresholds of static exposure can be modeled by an appropriate aging process with relevant statistics as indicated in the present work. (Reprints)