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CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

机译：CmOs片上静电放电保护电路，采用具有低EsD触发电压的四sCR结构

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Ming-dou Ker; Senior Member; Kuo-chun Hsu;
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年度 1994
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1. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits [J] . Ming-Dou Ker, Hsu K.-C. IEEE transactions on device and materials reliability . 2005,第2期

机译：CMOS集成电路中基于SCR的器件的片上静电放电保护设计概述
2. A novel on-chip electrostatic discharge (ESD) protection with common discharge line for high-speed CMOS LSIs [J] . Narita K., Horiguchi Y. IEEE Transactions on Electron Devices . 1997,第7期

机译：一种新颖的带有公共放电线的片上静电放电（ESD）保护，适用于高速CMOS LSI
3. An automated design system methodology and strategy for electrostatic discharge protection circuits in RF CMOS and BiCMOS silicon germanium technology [J] . Voldman SH., Strang SE., Jordan D. Journal of Electrostatics . 2003,第3a4期

机译：RF CMOS和BiCMOS硅锗技术中静电放电保护电路的自动化设计系统方法和策略
4. Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology [C] . Chang-Tzu Wang, Ming-Dou Ker, Tien-Hao Tang, IC Design and Technology, 2009. ICICDT '09 . 2009

机译：采用65nm全硅化CMOS技术的低泄漏静电放电保护电路
5. Low loading capacitance on-chip electrostatic discharges (ESD) protection circuits for gallium arsenide heterojunction bipolar transistor (HBT) radio frequency integrated circuits (RFIC). [D] . Ma, Yintat. 2004

机译：用于砷化镓异质结双极晶体管（HBT）射频集成电路（RFIC）的低负载电容片上静电放电（ESD）保护电路。
6. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications [O] . Yasunori Takeda, Kazuma Hayasaka, Rei Shiwaku, -1

机译：为低压可穿戴传感器应用而优化的超薄印刷有机TFT CMOS逻辑电路的制造
7. Electrostatic discharge protection for design for mixed-voltage CMOS I/O buffers [O] . Ming-dou Ker, Senior Member, Kun-hsien Lin 2002

机译：用于混合电压CmOs I / O缓冲器设计的静电放电保护
8. Susceptibility of On-Chip Protection Circuits to Latent Failures Caused by Electrostatic Discharges [R] . Neelakantaswamy, P. S., Turkman, I. R., Sarkar, T. K. 1986

机译：片上保护电路对静电放电引起的潜在故障的敏感性

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

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