Power-efficient metastability error reduction in CMOS flash A/D converters

摘要

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2/sup n/-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-/spl mu/m CMOS with measured metastability error rates of less than 10/sup -12/ errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10/sup -4/ errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2/sup n/-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs.