Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters

摘要

An architecture to reduce metastability error rates in highspeed flash A/D converters has been introduced. An 80-MHz, 7-bit A/D converter implemented in 1.2-μm CMOS has measured error rates of less than 10~(-12) errors/cycle. Similar error reduction with 2×2~n internal pipeline latches would require 3.48X more power to implement.