BEOL PROCESSING: Copper electroplating, CMP challenges grow more complex at 65-nm node and beyond

摘要

The back-end-of-line (BEOL) challenges facing fab teams as they develop and ramp the 65-, 45-, and 32-nm nodes will grow increasingly difficult and problematic with each successive process generation. Two critical areas of concern are copper electroplating and CMP. Can ultraclean plating baths capable of producing uniform, low-impurity, void-free films be developed that will help keep copper resistivity in check? How will on-line chemical metrology and the analysis of copper electroplating evolve and improve? Will future CMP tools minimize dishing and erosion adequately without damaging or degrading the mechanical strength and properties of porous low-k and ultra-low-k dielectric materials? Is electro-chemical-mechanical polishing (ECMP) a legitimate mainstream contender, and if so, when will it be implemented? What kinds of post-CMP cleaning and drying techniques will bebest suited to post-65-nm process recipes? These and other questions are addressed by this issue's Hot Button panel of BEOL experts from the chip-making and equipment communities.