Impact of electroplated copper thickness on copper CMP and Cu/Coral™ BEOL integration

摘要

A study was carried out to establish the impact of electrochemical plated (ECP) Cu thickness on the effect of dishing during Cu chemical mechanical planarization and the electrical and reliability performance of 0.13 μm Cu/Coral devices. The roughness of Cu films at the wafer edge was found to increase with increasing film thickness while it remained constant at the wafer centre. This resulted in different Cu grain morphology across the wafers. The reduction in sheet resistance (R_s) for the Cu film after annealing, as well as the as-deposited and post annealed film stresses were also found to be dependent on the ECP Cu thickness. As the thickness increased, the R_s reduction increased while the as-deposited and post annealed film stresses decreased. The different ECP Cu thickness did not show any significant difference in the amount of Cu dishing at the centre of the wafers. However, at the wafer edge, the Cu dishing amount was found to be significantly affected by the Cu thickness in which the amount of dishing increased as the thickness increased. The via chain, Kelvin via, M1 line and M2 line resistances also showed a strong dependence on the ECP Cu thickness. The thinnest Cu film of 0.7 μm gave the lowest results with the tightest spread for the four resistances tested. For the via chain and M1 line resistance, it was followed by the 1.0 μm Cu film and the 1.3 μm film yielded the worst data. In the case of Kelvin via and M2 line resistance, the thicker plated Cu films gave similar worse results. All the electrical results showed good coincidence with the Cu dishing data. The voltage ramp (v-ramp) data showed no significant difference in the electrical field leading to dielectric breakdown at both M1 and M2 lines for all the three types of ECP Cu thickness split.