Numerical analysis of Double Gate and Gate All Around MOSFETs with bulk trap states

摘要

This paper investigates the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using a numerical analysis of the two-dimensional coupled Boltzmann distribution-Poisson equations in which the traps effects have been considered. Using this numerical model, we have studied the effects of the defects on the scalability limits of DG and GAA MOSFETs and compared their performances. We have found that, the scaling capability of both architectures made in recrystallized silicon will be improved as the diameter (or silicon thickness for DG structure) of device is reduced, because the small device size decreases the defect density in the channel.