Impact of packaging stress on thinned 6T SRAM die

摘要

The impact of packaging stress on a thinned 65nm 6T SRAM cell bonded to a laminate is investigated. The mechanical stress resulting from this assembly operation is evaluated with an analytical model, and combined with the 4pt bending calibration yielding the transistors sensitivity to stress. The compact model is modified to take into account the resulting shift of the devices transcon-ductance as a function of the SRAM die thickness, and utilised to simulate the Access Disturb Margin (ADM) and Write Margin (WM) of the 6T SRAM cells. It is found that the WM is more sensitive to packaging stress due to the opposing effects of stress on NMOS and PMOS carrier mobilities, while the ADM is less affected due to its dependence on the contention between same-polarity devices.