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Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate

机译:专为低K Si和薄芯基板设计的低应力薄裸晶倒装芯片封装的结构和组装过程

摘要

Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
机译:提供了半导体管芯倒装芯片封装件和半导体管芯倒装芯片封装件组件,其中控制封装件/组件的某些特性以促进封装应力的管理。还提供了用于这种包装和包装部件的制造方法。例如,可以控制模具的厚度,以使由模具产生/经历的应力最小化。这样,将封装应力控制到合适的水平,以结合低K Si芯片和/或薄封装基板。另外,可以在半导体散热器倒装芯片封装的制造过程中将薄的管芯附接到散热器以增加刚度,以便于处理。

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