Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier

摘要

This paper investigates the reliability-tolerant design for ultra-thin-body (UTB) GeOI 6T SRAM cell and sense amplifiers. For UTB GeOI 6T SRAM cells, using high threshold voltage design significantly mitigates the read and hold static noise margin degradations due to NBTI and PBTI. Due to worse PBTI degradations, as stress (aging) time increases, GeOI current and voltage latch sense amplifiers show larger degradation in word-line to sense amplifier enable (SAE) delay (TWS) and sense amplifier sensing delay (TSA) compared with the SOI counterparts. Using WL to SAE self-timed sensing scheme mitigates the BTI induced delay degradation. A new reliability-tolerant sense amplifier with speed-up design is proposed for the first time to improve the PBTI dominated sensing delay for UTB GeOI sense amplifier.