FPGA Implementation and Mask Level CMOS Layout Design of Redundant Binary Signed Digit Comparator

摘要

In this paper a comparator is designed using Redundant Binary Signed Digit (RBSD) Number System. Radix-2 or signed binary digit number representations are of particular interest here. The redundant number system can be implemented by a digit set which has more digits in the set than the value of the radix and the set consists of digits {-1, 0, +1} This allows a given number tornhave more than one representation. Each digit within these digit sets with the exception of zero is present in both positive and negative polarities. The RBSD comparator is designed by VHDL as well as in Verilog and its RTL view is generated by its FPGA implementation. Keeping view the low power VLSI design, the gate level circuit is implemented by CMOS with the help of Verilog and its mask level Layout is designed and simulated. The FPGA Implementation is done by Libero IDE v6 environment, which is a product of Actel Inc. The mask level layout design is done by the high end EDA tool I.e. Microwind2. For the performance evaluation it is compared with binary comparator.