Comparator for digital value bits at CMOS voltage levels and bit with digital value at ECL voltage levels

摘要

The comparator has a CMOS decoder delivering 2n CMOS signals each corresponding to a different product of each of the n bits of the first digital value. There are 2n AND gates in ECL or CML technology which are associated with each of the 2n CMOS signals, and are connected to implement an OR function of the 2n bits that each correspond to a different product of the n bits of the ECL digital value. There is also a mechanism for deactivating the AND gates associated with the CMOS zero signals.