A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology.

摘要

The continuous trend in shrinking transistor size and reducing power supply voltage has prompted an increasing demand for low voltage analog circuit designs. A novel switched buffer switching technique in complimentary metal oxide semiconductor (CMOS) has been implemented for switched capacitor circuits in a low voltage low power 10-bit pipeline analog to digital converter (ADC) designed in 90 nanometer (nm) digital only CMOS technology with no analog enhancement.; This design demonstrates that a single standard digital power supply solution for a 10-bit pipeline ADC is possible at low supply voltages in deep sub-micron CMOS technology. Measurement results show that this design is capable of sampling at 12 MS/s achieving a peak signal to noise and distortion ratio (SNDR) of 52.6dB using a 1.2V supply. It consumes only 3.3mW.