Circuit for conversion of shifted differential ECL voltage levels to CMOS voltage levels with process compensation

摘要

A CMOS circuit for converting voltage levels between shifted differential ECL voltage level input signals and a CMOS voltage level signal. The ECL levels are referenced to the VDD voltage of the CMOS circuit and can be connected to ECL circuits that are connected between the CMOS VDD voltage and ground. The circuit has a pFET connected between a supply voltage and the output signal, and an nFET connected between the output signal and circuit ground. An inverted signal of the differential shifted ECL voltage input signals is connected to a gate of the nFET. A level shifting circuit connects the input signals to a gate of the pFET to ensure that it correctly drives the output signal when the input signals change logic levels.