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Warpage Analysis of Flip-Chip PBGA Packages Subject to Thermal Loading

机译:倒装芯片PBGA封装在热载荷作用下的翘曲分析

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The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260 $^{circ}hbox{C}$). In the experiments, a full-field shadow moirÉ was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhir''s die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moirÉ were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhir''s theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with-n noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.
机译:本文的目的是测量和模拟倒装芯片PBGA封装在热负荷(从室温到260 $ hcircbox {C} $)下的翘曲。在实验中,全场阴影波纹被用于测量在热加热和冷却条件下倒装芯片封装的基板和芯片表面上的实时平面外变形(翘曲)。有限元方法(FEM)和Suhir的模具装配理论,连同测得的材料数据(有机基材的弹性模量和热膨胀系数(CTE))一起,用于分析材料的热诱导变形。软件包以深入了解其机制。用于确定基板CTE的应变仪数据还表明,在热负荷下几乎没有弯曲应变。在温度负荷下记录了阴影波纹在包装的基材表面上的全场翘曲。还发现,在热加载期间,四个测试包装的零翘曲温度不同(导致室温下翘曲的变化),但是它们具有相似的翘曲率(翘曲相对于温度的斜率)。这可能是由于在回流焊温度下底部填充材料的蠕变和封装中的焊料凸点所致。无论零翘曲温度如何,都可以通过FEM和Suhir的理论很好地模拟或预测包装的翘曲。彻底研究了影响包装最大翘曲的关键材料性能(基材和底部填充材料的弹性模量和CTE)。已经发现,在这些材料特性中,用于底部填充的低弹性模量可以显着减小最大翘曲,而其CTE对翘曲的敏感性要低得多。此外,基板CTE仅对n个不顺应的底部填充物会影响包装的翘曲,而典型的基板弹性模量(10至30 GPa)对翘曲不敏感,除非其值低于几千兆帕斯卡。

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