Analytical Modeling of Electromigration Failure for VLSI Interconnect Tree Considering Temperature and Segment Length Effects

摘要

Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeling for EM effects for the interconnect tree has been studied recently to better EM signoff analysis. But the existing method cannot consider wires stressed under time-varying temperature, which is very typical for practical chip working conditions. In this paper, we develop the exact analytic model for the stress evolution of interconnect trees under different current density and varying segment length from the first principle. Due to the difficulty in obtaining the exact analytical solution, we focus on three-terminal wire in this paper. The stress evolution is modeled by two Korhonen's equations coupled through boundary conditions which are solved with the Laplace transformation technique. The new analytical EM model is further extended to consider the time-varying temperature stressing condition and initial non-zero residual stress. The proposed method is compared with the finite-element method (FEM) tool COMSOL, the recently proposed eigenfunction-based method, and the published EM simulator XSim. The comparison shows that the analytical solution agrees well with the results from the FEM numerical analysis. It uses much fewer terms compared to the eigenfunction method for the same accuracy. It also agrees very well with XSim, which is consistent with the previously reported measured results.