机译:顺序逻辑电路的进化设计的模块级三阶段方法
School of Urban Rail Transportation, Soochow University, Yangchenghu Campus,Jiexue Rd. No.8, Xiangcheng Area, Suzhou 215137, China Department of Computer Science, Shanghai Jiao Tong University, Shanghai 200240. China;
Department of Cardiology, The First Affiliated Hospital of Soochow University. Shizi Street No.188, Suzhou 215006, China;
Department of Computer Science, Shanghai Jiao Tong University, Shanghai 200240. China;
School of Urban Rail Transportation, Soochow University, Yangchenghu Campus,Jiexue Rd. No.8, Xiangcheng Area, Suzhou 215137, China;
Evolutionary approach; Module-level; Three-stage; Sequential circuits; Data mining; Frequently evolved blocks; Redundant states;
机译:顺序逻辑电路的进化设计的模块级三阶段方法
机译:时序逻辑电路进化设计的三步分解方法
机译:进化算法及其在时序逻辑电路设计中的应用
机译:在顺序逻辑电路设计中使用模块级可进化硬件方法
机译:时序电路的容错技术:设计级方法。
机译:稳健的生物回路设计:进化系统生物学方法
机译:通过进化多目标优化方法设计组合逻辑电路
机译:基于ROm的顺序电路(传统逻辑设计的另一种方法)。