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A module-level three-stage approach to the evolutionary design of sequential logic circuits

机译:顺序逻辑电路的进化设计的模块级三阶段方法

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In this study, we propose a module-level three-stage approach (TSA) to optimize the evolutionary design for synchronous sequential circuits. TSA has a three stages process, involving a genetic algorithm (GA), a pre-evolution, and a re-evolution. In the first stage, the GA simplifies the number of states and automatically searches the state assignment that can produce the circuit with small complexity. Then, the second stage evolves a set of high-performing circuits to acquire frequently evolved blocks, which will be re-used for more compact and simple solutions in the next stage. In this stage, a genetic programming (GP) is proposed for evolving the high-performing circuits and data mining is used as a finder of frequently evolved blocks in these circuits. In the final stage, the acquired blocks are encapsulated into the function and terminal set to produce a new population in the re-evolution. The blocks are expected to make the convergence faster and hence efficiently reduce the complexity of the evolved circuits. Seven problems of three types—sequence detectors, modulo-n counters and ISCAS89 circuits—are used to test our three-stage approach. The simulation results for these experiments are promising, and our approach is shown to be better than the other methods for sequential logic circuits design in terms of convergence time, success rate, and maximum fitness improvement across generations.
机译:在这项研究中,我们提出了一种模块级三阶段方法(TSA),以优化同步时序电路的演进设计。 TSA具有三个阶段的过程,涉及遗传算法(GA),预演化和重新演化。在第一阶段,GA简化了状态数量并自动搜索状态分配,该状态分配可以产生复杂度较小的电路。然后,第二阶段演化出一组高性能电路,以获取频繁演化的模块,这些模块将在下一阶段重新用于更紧凑,更简单的解决方案。在这一阶段,提出了遗传编程(GP)来发展高性能电路,并且数据挖掘被用作这些电路中频繁演化的块的发现者。在最后阶段,将获取的块封装到功能和终端集中,以在重新演化中产生新的总体。期望这些块使收敛更快,并因此有效地降低演进电路的复杂性。三种类型的七个问题(顺序检测器,模n计数器和ISCAS89电路)用于测试我们的三阶段方法。这些实验的仿真结果很有希望,并且在收敛时间,成功率和几代人之间的最大适应性改善方面,我们的方法被证明比顺序逻辑电路设计的其他方法更好。

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