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High performance poly-Si TFTs fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing

机译:使用脉冲激光退火和远程等离子体CVD以及低温处理技术制造的高性能多晶硅TFT

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摘要

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4/spl times/10/sup 16/ cm/sup -3/ by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO/sub 2//Si with the interface trap density of 2.0/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/ at 270/spl deg/C. Poly-Si TFTs were fabricated at 270/spl deg/C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm/sup 2//Vs for n-channel TFTs and 400 cm/sup 2//Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2/spl times/10/sup -10/ A//spl mu/m to 3/spl times/10/sup -13/ A//spl mu/m at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 /spl mu/m.
机译:讨论了在低温下制造多晶硅薄膜晶体管(poly-Si TFT)的关键技术。氢化的非晶硅膜通过30 ns脉冲XeCl准分子激光的照射而结晶。晶粒小于100nm。通过仅进行30秒的等离子体氢化,将多晶硅膜中的局部陷阱态的密度降低至4 / spl次/ 10 / sup 16 / cm / sup -3 /。使用网状电极的远程等离子体化学气相沉积(CVD)实现了SiO / sub 2 // Si的良好界面,界面陷阱密度为2.0 / spl乘以10 / sup 10 / cm / sup -2 / eV / sup -1 /在270 / spl deg / C。使用激光结晶,等离子体氢化和远程等离子体CVD以270 / spl℃/℃的速度制造多晶硅TFT。对于n沟道TFT,载流子迁移率是640cm / sup 2 // Vs,对于p沟道TFT是400cm / sup 2 // Vs。对于n沟道TFT,阈值电压为0.8 V;对于p沟道TFT,阈值电压为-1.5V。 n沟道多晶硅TFT的泄漏电流从2 / spl次/ 10 / sup -10 / A // spl mu / m降低到3 / spl次/ 10 / sup -13 / A // spl mu / m使用偏置长度为1 / spl mu / m的偏置栅电极在-5 V的栅极电压下实现m m

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