Gate Capacitances Behavior of Nanometer FD SOI CMOS Devices With HfO{sub}2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects Using 2-D Simulation

摘要

This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO{sub}2 high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step C{sub}(S(D)G)/C{sub}(GS) versus VG curve could be identified for the device with the 1.5-nm HfO{sub}2 gate dielectric due to the vertical and fringing displacement effects.