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Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances

机译:具有高K栅极介电层,金属栅电极区域和低边缘电容的半导体晶体管

摘要

A semiconductor structure and a method for forming the same. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.
机译:半导体结构及其形成方法。该结构包括:(i)包括沟道区的半导体衬底;(ii)半导体衬底上的第一和第二源/漏区;(iii)栅介电区;和(iv)栅电极区;(v)栅电极区域上的多个互连层,以及(vi)第一和第二空间。栅介电区设置在沟道区和栅电极区之间并与它们直接物理接触。栅电极区设置在栅介电区和互连层之间并与它们直接物理接触。第一空间和第二空间与栅电极区域直接物理接触。第一空间设置在第一源/漏区和栅电极区之间。第二空间设置在第二源/漏区和栅电极区之间。

著录项

  • 公开/公告号US7666746B2

    专利类型

  • 公开/公告日2010-02-23

    原文格式PDF

  • 申请/专利权人 JEFFREY PETER GAMBINO;

    申请/专利号US20080013514

  • 发明设计人 JEFFREY PETER GAMBINO;

    申请日2008-01-14

  • 分类号H01L21/00;

  • 国家 US

  • 入库时间 2022-08-21 18:49:06

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