MOSFET ESD Breakdown Modeling and Parameter Extraction in Advanced CMOS Technologies

摘要

This paper describes an approach for modeling the breakdown and snapback behavior of state-of-the-art MOSFET structures using equivalent-circuit description. Such models are required to enable circuit-level electrostatic discharge reliability simulations, which are a major challenge for the industry nowadays. Special attention is given to accurately describing the junction and gate leakage currents due to the increased tunneling generation in the scaled-down CMOS. Consistent parameter extraction procedures for the model parameters are described as well.