Characterization and Design Methodology for Low-Distortion MOSFET-C Analog Structures in Multithreshold Deep-Submicrometer SOI CMOS Technologies

摘要

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V{sub}(th) deep-submicrometer 0.12-μm silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25℃-220℃) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.