Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High- $k$ Trapping Layer

摘要

A time-dependent analytical method based on effective traps in a modified equivalent oxide thickness (EOT) model has been proposed for Flash memory studies, which reflects the effective vertical trap location. The effects of effective trap location and potential on memory properties have also been investigated using Si3N4, HfO2, and ZrO2 devices with the same physical structure as well as with the same equivalent effective trap structure. It was found that effective trap locations varied, depending on the material being concentrated from the Si substrate at 3.8-4.1 nm for ZrO2, 4.2-4.6 nm for HfO2, and 7-8 nm for Si3N4. Vertical trap location was found to affect the programming/ erasing (P/E) properties of different devices with the same physical structure, while trap potential depth was found to affect the P/E properties of those with the same total EOT and effective trap location. Physical trap generation by repetitive P/E cycling is also studied in this paper.