Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

摘要

We propose an extraction technique for parasitic resistance $(R_{P})$ with $L$-, $V_{rm GS}$-, and $V_{rm DS}$-dependences even for large $V_{rm DS}$ in amorphous indium–gallium–zinc oxide thin-film transistors ($a$-IGZO TFTs), by employing $I_{rm DS}$–$V_{rm GS}$ characteristics (as a function of $V_{rm DS}$ ) of two $a$-IGZO TFTs with different channel lengths ( $L_{1}$ and $L_{2}$ ). The resistance between the source and drain is modeled as an effective total resistance defined as $R_{T}^{ast} equiv V_{rm DS}/I_{D}$ for all over the drain bias $V_{rm DS}$ including both linear and saturation regions. The proposed method can be efficiently employed to model dc $I$–$V$ characteristics and extract the parasitic resistance in $a$-IGZO TFTs even with short channel lengths, because the internal drain voltage $(V_{rm DS}^{prime})$ is accurately calculated as a function of $V_{rm GS}$, $V_{rm DS}$, and $L$ by deembedding the voltage drop across the parasitic resistance $R_{P}$.