A Bottom-Gate Indium-Gallium-Zinc Oxide Thin-Film Transistor With an Inherent Etch-Stop and Annealing-Induced Source and Drain Regions

摘要

The resistivity of an indium-gallium–zinc oxide (IGZO) thin film was found to depend on not only the conditions of its thermal annealing but also the oxygen-permeability of the cover film during the heat treatment. Based on this observation, a technology for constructing a bottom-gate IGZO thin-film transistor with annealing-induced source and drain (S/D) regions is proposed and demonstrated. The S/D and channel regions with this device architecture are capped, respectively, by impermeable and permeable covers. During a subsequent heat treatment in an oxidizing atmosphere, the resistivity of the S/D regions is greatly reduced; while the channel region, being exposed to the oxidizing atmosphere through the permeable cover, retains its highly resistive character. The permeable cover protects the channel region by serving additionally as an inherent back-channel etch-stop during the etching of the impermeable cover. No patterning is needed to realize this etch-stop, implying a lower manufacturing cost.