A transistor comprises: inversion epitaxial layer (11) on silicon substrate (10); trench over the inversion epitaxial layer; reverse spacers (13) on sidewalls of the trench; gate electrode (16) above the inversion epitaxial layer between the reverse spacers; spacers on the sidewalls of the gate electrode; pocket-well regions; lightly-doped drain (LDD); source and drain regions (19); and silicide layer (20) positioned on the gate electrode and the source and drain regions. Transistor comprises: inversion epitaxial layer on a silicon substrate; trench over the inversion epitaxial layer; reverse spacers on sidewalls of the trench; gate electrode above the inversion epitaxial layer between the reverse spacers; spacers on the sidewalls of the gate electrode; pocket-well regions under opposite sides of the gate electrode; lightly-doped drain regions positioned adjacent respective ones of the pocket-well regions; source and drain regions positioned adjacent the LDD regions; and a silicide layer positioned on the gate electrode and the source and drain regions. The source and drain regions have a larger thickness than the LDD regions. An independent claim is also included for a method of fabricating a transistor, comprising: forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; forming a silicon epitaxial layer over the inversion epitaxial layer; removing the hard mask to form a trench through the silicon epitaxial layer; filling the trench with an insulating layer; etching the insulating layer to form reverse spacers on sidewalls of the trench; forming a gate electrode over the reverse spacers; performing ion implantation using the gate electrode as a mask to form pocket-well regions and LDD regions; forming spacers on sidewalls of the gate electrode; performing ion implantation using the gate electrode and the spacers as a mask to form source/drain regions; and forming a silicide layer on the gate electrode and the source and drain regions.
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