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Characterization of oxide trap and interface trap creation during hot-carrier stressing of n-MOS transistors using the floating-gate technique

机译:使用浮栅技术在n-MOS晶体管的热载流子应力过程中表征氧化物陷阱和界面陷阱的形成

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摘要

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I/sub g/-V/sub g/ characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I/sub g/-V/sub g/ characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I/sub g/-V/sub g/ measurements.
机译:已经开发出一种技术来区分界面状态和常规n沟道MOS晶体管中的氧化物陷阱电荷。使用浮栅技术在应力损坏之前和之后测量栅极电流。结果表明,与低栅极电压应力产生和填充氧化物陷阱相比,I / sub g / -V / sub g /特性的变化与中栅极电压下界面陷阱的产生相比,表现出明显的差异。应力条件,可以通过I / sub g / -V / sub g /特性来识别热载流子损坏。根据在I / sub g / -V / sub g /测量期间所创建的接口陷阱的占用率随栅极电压的变化来解释差异。

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