首页> 外文期刊>IEEE Electron Device Letters >Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner
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Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner

机译:具有硅碳源极/漏极和拉伸应力衬里的25nm栅极长度薄体nMOSFET的增强应变效应

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We report the demonstration of 25-nm gate-length LG strained nMOSFETs featuring the silicon-carbon source and drain (Si1-yCyS/D) regions and a thin-body thickness T body of ~18 nm. This is also the smallest reported planar nMOSFET with the Si1-yCyS/D stressors. Strain-induced mobility enhancement due to the Si1-yCy S/D leads to a significant drive-current IDsat enhancement of 52% over the control transistor. Furthermore, the integration of tensile-stress SiN etch stop layer and Si1-yC yS/D extends the IDsat enhancement to 67%. The performance enhancement was achieved for the devices with similar subthreshold swing and drain-induced barrier lowering. The Si1-y CyS/D technology and its combination with the existing strained-silicon techniques are promising for the future high-performance CMOS applications
机译:我们报告了具有25nm栅极长度的LG应变nMOSFET的演示,该晶体管具有硅碳源和漏(Si1-yCyS / D)区域以及约18 nm的薄体厚度T body。这也是报告的最小的带有Si1-yCyS / D应力源的平面nMOSFET。由于Si1-yCy S / D引起的应变诱导的迁移率提高导致驱动电流IDsat比控制晶体管提高了52%。此外,拉应力SiN蚀刻停止层和Si1-yC yS / D的集成将IDsat增强扩展到67%。对于具有类似亚阈值摆幅和漏极引起的势垒降低的器件,可以实现性能增强。 Si1-y CyS / D技术及其与现有应变硅技术的结合对于未来的高性能CMOS应用是有前途的

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