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100 Å Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime

机译：100Å互补硅化物源极/漏极薄体mOsFET，适用于20nm栅极长度范围

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Jakub Kedzierski; Peiqi Xuan; Erik H. Anderson; Jeffrey Bokor; Tsu-jae King; Chenming Hu;
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年度 2008
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1. Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner [J] . Kah-Wee Ang, King-Jien Chui, Chih-Hang Tung, IEEE Electron Device Letters . 2007,第期

机译：具有硅碳源极/漏极和拉伸应力衬里的25nm栅极长度薄体nMOSFET的增强应变效应
2. Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner [J] . Kah-Wee Ang, King-Jien Chui, Chih-Hang Tung, IEEE Electron Device Letters . 2007,第4期

机译：具有硅碳源极/漏极和拉伸应力衬里的25nm栅极长度薄体nMOSFET的增强应变效应
3. Dopant-Segregated Schottky Source/Drain Double-Gate MOSFET Design in the Direct Source-to-Drain Tunneling Regime [J] . Vega R. A., Liu K., Liu T.-J. K. Electron Devices, IEEE Transactions on . 2009,第9期

机译：直接源极到漏极隧穿区中的掺杂隔离肖特基源极/漏极双栅MOSFET设计
4. Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime [C] . Kedzierski, J., Xuan, Electron Devices Meeting, 2000. IEDM Technical Digest. International . 2000

机译：互补的硅化物源极/漏极薄体MOSFET，用于20 nm栅极长度范围
5. Complementary silicide thin-body silicon-on-insulator CMOS devices. [D] . Kedzierski, Jakub Tadeusz. 2001

机译：互补硅化物薄体绝缘体上硅CMOS器件。
6. A quasi-ballistic drain current charge and capacitance model with positional carrier scattering dependency valid for symmetric DG MOSFETs in nanoscale regime [O] . Vyas R. Murnal, C. Vijaya 2019

机译：具有位置载流子散射相关性的准弹道漏电流电荷和电容模型对纳米级对称DG MOSFET有效
7. A Study of Gate Length and Source-Drain Bias on Electron Transport Properties in SiC Based MOSFETs Using Monte Carlo Method [O] . H. Arabshahi 2013

机译：用monte Carlo方法研究siC基mOsFET中电子输运特性的栅长和源漏偏差

100 Å Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime

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