首页> 外文期刊>Electron Device Letters, IEEE >A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer
【24h】

A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer

机译:具有全方位栅多晶硅纳米线和HfAlO陷阱层的新型电荷陷阱型存储器

获取原文
获取原文并翻译 | 示例

摘要

Hf-based charge-trapping (CT) layers, including $hbox{HfO}_{2}$ and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a $hbox{HfO}_{2}$ trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations.
机译:基于Hf的电荷陷阱(CT)层,包括$ hbox {HfO} _ {2} $和HfAlO,被用于制造具有全栅(GAA)多晶硅纳米线通道的CT型存储器。结果表明,与传统的平面方案相比,GAA配置可以大大提高编程/擦除效率。还表明,与具有$ hbox {HfO} _ {2} $俘获层的对应物相比,将Al结合到电介质中可以进一步改善保留和耐久特性。假定介导了铝结合的介电膜的再结晶的延迟是造成这些现象的原因。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号