Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices

摘要

Trap-layer-engineered poly-Si nanowire silicon–oxide–nitride–oxide–silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxideitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.