Constant power consumption design of novel differential logic gate for immunity against differential power analysis


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Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND-NAND, and OR-NOR which can be easily extended for n-bit inputs. The design effort is minimal as the structure is such that AND-NAND design can be used to obtain OR-NOR function by just changing the placement of inputs. These gates have 0.46x less propagation delay, and 3.7x higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V.
机译:差分功率分析(DPA)方法通常用于非侵入性侧通道攻击,以侵入系统。这项研究提出了一种新颖的基本门DPA免疫设计,该设计显示了自相关的密集分布和60%左右的显着强度。该设计具有高度规则的结构,对于差分输出,AND-NAND和OR-NOR,其评估路径完全相似,可以轻松扩展为n位输入。由于这种结构的设计工作量很小,因此仅更改输入的位置即可将AND-NAND设计用于获得OR-NOR功能。与其他已发表的作品相比,这些门的传播延迟减少了0.46倍,功耗降低了3.7倍。使用带有1.8J电源的TowerJazz CMOS 180 nm技术的Cadence工具对设计进行仿真。


  • 来源
    《Circuits, Devices & Systems, IET》 |2019年第1期|103-109|共7页
  • 作者

    Saini Harjap; Gupta Anu;

  • 作者单位

    BITS Pilani, Dept Elect & Elect Engn, Pilani, Rajasthan, India;

    BITS Pilani, Dept Elect & Elect Engn, Pilani, Rajasthan, India;

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  • 入库时间 2022-08-18 04:12:14


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